The invention relates generally to self-configuring modular electronic systems and, particularly, to a computer system having a data and address bus with multiple lines and having several addressable modules electrically connected to the bus via respective module lines.
An electronic system of this type is known from EP 0 491 480 A2. In order to address electronic modules in computers, a series of bus line pairs between successive slots are interchanged in accordance with a binary pattern such that each slot has an unmistakable coding. During an initialization phase of the computer, a bit pattern of predetermined signals is applied to the bus line pairs. Due to the reversal of the bus line pairs, each slot then receives a different bit pattern such that each station is able to identify its assigned slot and thus receives an unmistakable address.
U.S. Pat. No. 4,727,475 describes a self-configuring modular computer system with a central processing unit and several modules that are connected to a bus. A call signal generated by the central processing unit is received by the module located closest to the central processing unit. This module applies an identification signal to the bus, with the central processing unit generating a base address for the module. This process is repeated until all modules have been assigned a bus base address. This system requires that each module have an individual identifier at the beginning of the address assignment process such that all modules can be individually addressed sequentially.
DE 33 47 357 A1 describes a similar device for assigning addresses to plug-in modules. In this case, a characterizing module identifier is applied to each module. In addition, each module is given a slot identifier. During initialization, all modules are called by means of the slot identifier and give the control unit their respective module identifiers. The control unit then assigns the modules their relevant address by addressing the slot identifier with the relevant address being used for the additional exchange of data.
DE 29 32 868 A1 describes a data processing circuit arrangement with a central processing unit to which several peripheral devices are connected. Each peripheral unit has an electronically programmable address memory, with each address memory being connected to a central processing unit via a separate enabling line that is only assigned to the respective address memory. Each individual peripheral unit can be addressed and assigned an address by the central processing unit via this enabling line.
DE 39 38 018 C2 describes an information processing system and a method for determining its configuration. Each slot for modules has separate connections, the potential levels of which process a xe2x80x9cslot-ID-signalxe2x80x9d in order to allow the individual addressing of the respective slot. A certain address can then be assigned to each module at the corresponding slot by a central processing unit.
DE 44 21 344 A1 describes a supplementary card for a computer which has a predetermined digital hardware identification. This identification makes it possible to address each individual supplementary card and assign an address for a bus system to each card by a central processing unit.
The entire disclosures of the aforementioned references are incorporated herein by reference.
In known systems, the configuration and the identification of the connected modules is realized by means of reversed bus lines, by assigning different initialization addresses to the individual modules, or by providing additional lines that are assigned to the respective modules. For this reason, a self-configuring modular electronic system that has a simple design and that makes it possible to connect a series of addressable modules to a common bus, where all modules may also be absolutely identical, is desired.
The present invention meets the above needs and overcomes the deficiencies of the prior art by providing a self-configuring modular electronic system that has a simple design and that makes it possible to connect a series of addressable modules to a common bus, where all modules may also be absolutely identical.
The invention is based on the idea of routing an identification signal from module to module, and to change this identification signal in defined fashion during the routing. So that, each module receives a different identification signal that unmistakably differentiates it from the remaining modules and, for example, may be used for addressing purposes.
The identification signal is changed with the aid of arithmetic devices that, for example, may consist of full adders and respectively add a signal that corresponds to a number (e.g., a xe2x80x9c1xe2x80x9d) to the identification signal. The result of the addition is routed to the next bus terminal or the next module such that a separate address, e.g., an address that is incremental by xe2x80x9c1xe2x80x9d (address number), can be assigned to each module.
In this case, the arithmetic devices may be directly arranged on the bus between respectively adjacent slots and/or integrated into the individual modules.
The invention can be used for configuring or addressing individual components of a computer system, e.g., individual microprocessors, network cards, memory cards, etc., which are connected to the corresponding bus terminals. However, it is explicitly noted that the invention may also be used in any given electronic system in which several modules to be identified are connected to one another via a line system.
Devices for electrically connecting the modules to the data and address bus, e.g., sockets or terminal strips, are preferably provided on the individual bus terminals.
The spatial arrangement of the individual modules may be selected differently. According to one variant, the modules are arranged adjacent to one another in a single plane on a printed-circuit board. Alternatively, it is also possible to xe2x80x9cstack several modules one atop the other,xe2x80x9d with the individual modules being interconnected and to the bus via electronic connecting means, e.g., sockets. Such a xe2x80x9cthree-dimensionalxe2x80x9d arrangement of the individual modules makes it possible to achieve a high component density and thus contributes to the additional miniaturization of the system. In addition, it is possible to arrange several such stacks consisting of individual modules adjacent to one another.
The individual modules may consist of independent central processing units, independent computers, peripheral devices, memory modules or the like, all of which communicate with one another via a common system. The individual modules may also have their own xe2x80x9cintelligence.xe2x80x9d However, this is not absolutely imperative. In particular, it is possible to use several absolutely identical modules.
Alternatively, the invention may comprise various other methods and systems.
Other objects and features will be in part apparent and in part pointed out hereinafter.